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An SR latch is one of the simplest kinds of electronic memory that can be built with logic gates. See <en.wikipedia.org...> for more information.
Set the evidence for 'R' (Reset) and 'S' (Set) to 'False' for all time steps. Then enter a 'True' in 'S' (Set) for time step 3. The 'output' of NOR1 will be locked to True thereafter. (You can then set 'R' to 'True' in a later timestep to clear it.) Requires GeNIe.